Clock

The chip requires an external 26 MHz clock, which is generated by TCXO, to provide reference frequency for RF and baseband PLL. In order to ensure the stable operation of the PLL when the chip is booted, the 26 MHz clock should work stably within10 ms after the main and IO domains are powered.

The chip supports RTC crystal input. RTC crystal is usually driven by an on-chip 32.768 kHz oscillator, which connects to an external 32.768 kHz crystal. The chip also supports external RTC clock input. The input signal amplitude should be 0.9 V to 1.98 V, and the input signal frequency should be 32.768 kHz. The RTC clock frequency offset must be less than 20 ppm.

If the main power supply and IO power supply fail and a backup battery is connected to V_BACK, the baseband, RF and CPU do not work, while RTC keeps running to provide time reference for the receiver. This operating mode is called RTC time keeping mode. Under this mode, the relevant data are saved in Retention RAM for GNSS hot start.

RTC time keeping mode is a prerequisite for GNSS hot start. Under this mode, RTC provides time information and Retention RAM provides ephemeris and almanac information. If you do not need GNSS hot start function, connect RTC_O to ground. In the AGNSS-based system, if time and ephemeris are provided through network as assistance, RTC is not necessary.